The present invention is directed to signal processing system and electrical circuits.
Over the last few decades, we have witness a continued increase in processing power and speed of computing device and electronics. Machines are expected to perform a large number of operations quickly. Similarly, data are transferred at higher and higher speed. An important aspect of operating electronic devices and communication systems, especially in the digital domain, is to provide reference clock signal that provide coordination of various circuits. Without accurate and reliable clock signals, high speed computation and communication are not possible.
With complicated ICs operating at high speeds, it is important to provide mechanism to lock clock signals. Over the past, phase-locked loop (PLL) and delay-locked loop (DLL) have been used to provide synchronization. DLL systems are implemented using delay lines, as opposed to oscillator in PLL systems.
In addition to provide synchronization, DLL systems have also been used to change phase of a clock signal, provide clock recovery, deskew, and in many other applications. Over the past, various types of DLL systems have been proposed and implemented. Unfortunately, existing DLL systems are often inadequate, especially in high speed operation. Therefore, new and improved DLL systems are desired.